1. Field of the Invention
The present invention relates generally to an active-matrix addressed liquid crystal display (LCD) unit, and more specifically to such a unit having a pixel data rearrangement circuit for ordering incoming pixel data to a predetermined format in order to properly drive an LCD panel.
2. Description of Related Art
LCDs have found extensive uses in a variety of electronic devices such as television receivers, personal computers, personal digital assistances (PDAs), mobile telephone terminals, picture monitors, and so on. Among others, active-matrix addressed LCDs have widely utilized, which are provided with a plurality of active elements (switching elements) respectively assigned to pixel electrodes for controlling application of voltages thereto. The active element is typically a thin film transistor (TFT). The active-matrix addressed LCD has distinct features of high resolution, a wide viewing angle, a high contrast, multi-gradation, etc.
With the developments of LCD manufacturing technology, it is a current tendency that the LCD panel becomes large while maintaining or increasing pixel density. Accordingly, the number of pixels per line increases and it becomes necessary to increase a timing clock frequency. However, as the timing clock becomes higher, the conventional LCD device has encountered the difficulties that the manufacturing cost of the source drivers becomes higher and that EMI (electromagnetic interference) has become noticeable.
In order to address the above-mentioned problems, it has been proposed to divide the source drivers into two groups to which the pixel data are applied in parallel. Therefore, it is possible to halve the clock frequency. Such proposal is disclosed in Laid-Open Japanese Patent Applications Nos. 5-210359 and 10-207434.
Before turning to the present invention, it is deemed advantageous to briefly described, with reference to FIG. 1, the conventional technology disclosed in the aforesaid Japanese Patent Application No. 5-210359.
FIG. 1 is a block diagram showing an LCD panel 2 and peripheral blocks. The LCD panel 2 carries a plurality of source drivers 3 at the periphery thereof for driving TFTs provided in matrix in the panel 2. The source drivers 3 are divided into two groups: one group 3L is assigned to the left half of the LCD panel 2 and the other group 3R to the right half of the panel 2. One path of pixel data is applied to an interface 4 at which the incoming pixel data is divided into two-path pixel data S1 and S2 using a clock CK1. This clock CK1 is also applied to a frequency divider 5 that halves the clock rate of the clock CK1 and issues the frequency (rate) halved clock as a clock CK2.
A controller 6 is supplied with the two-path pixel data S1 and S2 using the clock CK2, and applies these data to the source driver groups 3L and 3R as S1U and S2U, respectively. In addition, the controller 6 prepares a sampling start signal SP using the pixel data S1 or S2, and applies the signal SP to the leading source driver of each of the driver groups 3L and 3R. Thus, the pixel data S1U and S2U are displayed in parallel. As mentioned above, this prior art features that the source drive timing clock can be halved. This means that a large LCD panel can be driven without increase in the timing clock, and at the same time, the EMI problems can be reduced.
As mentioned above, the aforesaid prior art is supplied with a single path pixel data and then divides the same into two-path pixel data for the left and right source drivers 3L and 3R. Meanwhile, it is typical that the LCD panel manufacturer produces, as a unit, the LCD panel 2, the interface 4, and the controller 6. Therefore, the LCD device makers, who purchase such LCD panel units, are undesirably obliged to prepare the pixel data that has been previously determined by the LCD panel manufacturer, which reduces the degree of freedom in circuit design. It is not rare that the LCD device maker wishes to apply a plurality of paths of pixel data with different data formats to the LCD panel unit. However, the above-mentioned prior art is unable to comply with such requirements of the users. Other prior art, the Laid-Open Japanese Patent Application No. 10-207434, suffers from the same difficulties as mentioned above.